Dependable Multicore Architectures at Nanoscale

This book provides comprehensive coverage of the dependability challenges in today's advanced computing systems. It is an in-depth discussion of all the technological and design-level techniques that may be used to overcome these issues and analyzes various dependability-assessment methods. The impact of individual application scenarios on the definition of challenges and solutions is considered so that the designer can clearly assess the problems and adjust the solution based on the specifications in question.

The book is composed of three sections, beginning with an introduction to current dependability challenges arising in complex computing systems implemented with nanoscale technologies, and of the effect of the application scenario.

The second section details all the fault-tolerance techniques that are applicable in the manufacture of reliable advanced computing devices. Different levels, from technology-level fault avoidance to the use of error correcting codes and system-level checkpointing are introduced and explained as applicable to the different application scenario requirements.

Finally the third section proposes a roadmap of future trends in and perspectives on the dependability and manufacturability of advanced computing systems from the special point of view of industrial stakeholders.

Dependable Multicore Architectures at Nanoscale showcases the original ideas and concepts introduced into the field of nanoscale manufacturing and systems reliability over nearly four years of work within COST Action IC1103 MEDIAN, a think-tank with participants from 27 countries. Academic researchers and graduate students working in multi-core computer systems and their manufacture will find this book of interest as will industrial design and manufacturing engineers working in VLSI companies.

Marco Ottavi is currently an Associate Professor at the University of Rome Tor Vergata. He received the Laurea degree (M.Sc.) in Electronic Engineering from the University of Rome La Sapienza in 1999 and the Ph.D. in Telecommunications and Microelectronics from the the University of Rome Tor Vergata in 2004. From 2003 to 2007 he was visiting scholar and research associate at Northeastern University in Boston (USA). In 2006 he was invited to Sandia National Laboratories in Albuquerque (USA) as a visiting research scholar. In 2007 he became a U.S. permanent resident through the prestigious EB1 visa intended for outstanding researchers. From 2007 to 2009 he was with Advanced Micro Devices (AMD) in Boxborough (USA) as a Senior Design Engineer. In 2009 he joined the University of Rome Tor Vergata as the recipient of a "Rientro dei Cervelli" (reverse brain drain) fellowship awarded by the Italian Ministry of University. His research focuses on reliability of electronic systems at nanoscale. On these topics he published 6 books chapters and about 100 contributions to international conferences, peer-reviewed journals in which he serves also as organizer and reviewer. From 2011 he is the chair of the European project COST IC1103 MEDIAN (Manufacturable and Dependable Multicore Architectures at Nanoscale). He is senior member of IEEE.

Dimitris Gizopoulos is Professor at the Department of Informatics & Telecommunications, of National and Kapodistrian University of Athens where he leads the Computer Architecture Laboratory since 2011. Previously, he led for ten years the Computer System Laboratory of the University of Piraeus. His research focuses on the dependability, performance and power of computer architectures. Gizopoulos has published more than 150 papers in peer reviewed IEEE and ACM journals and conferences, is an inventor of US patents, author of a book and editor of two more on testing and fault tolerance. He served as associate editor of IEEE Transactions on Computers IEEE Transactions on VLSI Systems, IEEE Design & Test of Computers Magazine and currently serves as associate editor in IEEE Transactions on Sustainable Computing and Springer's JETTA. He served several times as member of the Steering, Organizing and Program Committees, and as General and Program Chair of major IEEE and ACM conferences. He is an IEEE Fellow and a Golden Core Member of IEEE Computer Society. He participated in and led several research and development projects funded by the EU, the Greek government and private funds from companies. Gizopoulos is the University of Athens lead in the CLERECO FP7 project and the UniServer H2020 project, and coordinator of the HOLISTIC and DIaSTEMA projects (both funded by EU and the Greek government), a member of HiPEAC NoE and the Vice-chair of the MEDIAN ESF-funded COST Action.

Salvatore Pontarelli received the master Degree at university of Bologna in 2000. In 2003 takes its PhD degree in microelectronics and telecommunications from the University of Rome Tor Vergata. Currently, he works as Senior Hardware Design Engineer at CNIT (Italian Consortium of telecommunication), in the research unit of University of Rome Tor Vergata. His research mainly focuses on error detection and correction codes, arithmetic self checking circuits and reconfigurable architectures. He is also interested in the use of reconfigurable hardware for high speed network monitoring. In the past Dott. Pontarelli has worked with the National Research Council (CNR), the Department of Electronic Engineering of University of Rome Tor Vergata, the Italian Space Agency (ASI), the Univeristy of Bristol and has been consultant for various italian and european companies for projects related to digital design and to fault tolerance in digital systems. He partecipates in several national and EU funded research program (ESA, FP7 and H2020) and in 2011 he has been awarded of the prestigious CISCO research Award fora study on the use of Bloom filter for error detection in Ternary CAM.

Introduction.- Part I: Current Challenges.- Manufacturing Challenges.- Dependability Challenges.- An Application Scenario.- Part II: Solutions.- Manufacturability Solutions.- Dependability Solutions.- Application-Specific Solutions.- Part III: Roadmap.- Technological Road Map.- Architectural Roadmap.